View ISL5422209_4829073.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NS ESI G W D ART NE NT P FO R D ED LA C EM E EN M M D RE P E CO A Data Sheet E OT R MMEND SL54222 N I CO RE
(R)
ISL54222
May 27, 2009 FN6835.1
High-Speed USB 2.0 (480Mbps) Multiplexer
The Intersil ISL54222 is a single supply dual 2:1 multiplexer that can operate from a single 1.8V to 3.3V supply. It contains two SPDT (Single Pole/Double Throw) switches configured as a DPDT. The part was designed for switching or routing of USB High-Speed signals and/or USB Full-speed signals in portable battery powered products. The 5.5 switches can swing rail-to-rail and were specifically designed to pass USB full speed data signals that range from 0V to 3.3V and USB high speed data signals that range from 0V to 400mV with a single supply as low as 1.8V. They have high bandwidth and low capacitance to pass USB high speed data signals with minimal distortion. The part can be used in Personal Media Players and other portable battery powered devices that need to route USB high-speed signals and/or full-speed signals to different transceiver sections of the device while connected to a single USB host (computer). The digital logic inputs are 1.8V logic compatible when operated with a 1.8V to 3.3V supply. The ISL54222 has an output enable pin to open all the switches. It can be used to facilitate proper bus disconnect and connection when switching between the USB sources. The ISL54222 is available in 10 Ld 1.8mmx1.4mm TQFN, 10 Ld TDFN and 10 Ld MSOP packages. It operates over a temperature range of -40 to +85C.
Features
* High-Speed (480Mbps) and Full-Speed (12Mbps) Signaling Capability per USB 2.0 * 1.8V Logic Compatible * Enable Pin to Open all Switches * Power OFF Protection * D-/D+ Pins are Overvoltage Tolerant to 5.5V * -3dB Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . 782MHz * Low ON Capacitance. . . . . . . . . . . . . . . . . . . . . . . . 6.5pF * Low ON-Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 * Single Supply Operation (VDD) . . . . . . . . . . . . 1.8V to 3.3V * Available in TQFN, TDFN, and MSOP Packages * Pb-Free (RoHS Compliant) * Compliant with USB 2.0 Short Circuit and Overvoltage Requirements Without Additional External Components
Applications
* MP3 and other Personal Media Players * Cellular/Mobile Phones * PDA's * Digital Cameras and Camcorders * USB Switching
Application Block Diagram
CONTROLLER VDD
ISL54222
SEL VBUS USB CONNECTOR LOGIC CIRCUITRY
OE
D-
HSD1DHSD1+
USB HIGH-SPEED OR FULL-SPEED TRANSCEIVER #1
D+
D+
HSD2HSD2+ GND
GND
USB HIGH_SPEED OR FULL-SPEED TRANSCEIVER #2 PORTABLE MEDIA DEVICE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL54222 Pinouts
ISL54222 (10 LD 1.8 X 1.4 TQFN) TOP VIEW
HSD17 OE 8 LOGIC CONTROL VDD 9 HSD26 5 4 3 1 HSD1+ 2 HSD2+ GND 5 6 DDGND D+ SEL 1 LOGIC CONTROL 10 VDD 9 8 OE
ISL54222 (10 LD MSOP, TDFN) TOP VIEW
HSD1+
2 3 4
SEL 10
HSD2+
HSD1-
D+
7
HSD2-
NOTE: 1. Switches Shown for SEL = Logic "1" and OE = Logic "0".
Truth Table
OE 0 0 1 SEL 0 1 X HSD1-, HSD1+ ON OFF OFF HSD2-, HSD2+ OFF ON OFF
Pin Descriptions
PIN NAME VDD GND SEL OE DESCRIPTION Power Supply Ground Connection Select Logic Control Input Bus Switch Enable
Logic "0" when 0.5V, Logic "1" when 1.4V with a 1.8V to 3.3V Supply.
D+, D-, HSDx+, HSDx- USB Data Port
Ordering Information
PART NUMBER ISL54222IRUZ-T* (Note NOTES:) ISL54222IRTZ (Note 3) ISL54222IRTZ-T* (Note 3) ISL54222IUZ (Note 3) ISL54222IUZ-T* (Note 3) ISL54222IRUEVAL1Z J 4222 4222 54222 54222 Evaluation Board PART MARKING TEMP. RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 10 Ld 1.8 x 1.4mm TQFN (Tape and Reel) 10 Ld 3x3 TDFN 10 Ld 3x3 TDFN (Tape and Reel) 10 Ld MSOP 10 Ld MSOP (Tape and Reel) PKG. DWG. # L10.1.8x1.4A L10.3x3A L10.3x3A M10.118 M10.118
*Please refer to TB347 for details on reel specifications. NOTES: 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN6835.1 May 27, 2009
ISL54222
Absolute Maximum Ratings
VDD to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3.5V Input Voltages HSD2x, HSD1x (Note 4). . . . . . . . . . . . . . . . . . . . . - 0.3V to 6.0V SEL, OE (Note 4) . . . . . . . . . . . . . . . . . . . -0.3V to ((VDD) + 0.3V) Output Voltages D+, D- (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Continuous Current (HSD2x, HSD1x) . . . . . . . . . . . . . . . . . . 40mA Peak Current (HSD2x, HSD1x) (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 100mA ESD Rating: Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kV
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 10 Ld TQFN Package (Note 5) . . . . . 160 N/A 10 Ld TDFN Package (Notes 6, 7). . . . 55 18 10 Ld MSOP Package (Note 5) . . . . . . 165 N/A Maximum Junction Temperature (Plastic Package). . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to +150C
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . 1.8V to 3.3V Logic Control Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. Signals on HSD1x, HSD2x, D+, D- exceeding GND by specified amount are clamped. Signals on OE and SEL exceeding VDD or GND by specified amount are clamped. Limit current to maximum current ratings. 5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 7. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications - 1.8V to 3.3V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V,
VOEH = 1.4V, VOEL = 0.5V, (Note 8), Unless Otherwise Specified. PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG VDD = VDD, SEL = 0V or VDD, OE = 0V Full 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF VDD = 3.3V, VIN = 3V, RL = 50, CL = 50pF (see Figure 1) VDD = 3.3V, VIN = 3V, RL = 50, CL = 50pF (see Figure 1) 25 25 50 33 ns ns 0 -15 -20 -20 -25 -15 -20 -20 -25 5.5 0.072 0.44 0.35 2.5 0.26 1.65 0.005 VDD 8 10 0.5 0.55 1.2 1.3 15 20 20 25 15 20 20 25 0.025 0.5 V nA nA nA nA nA nA nA nA A A TEST CONDITIONS TEMP MIN (C) (Notes 9, 10) TYP MAX (Notes 9, 10) UNITS
ON-Resistance, rON (High-Speed) VDD = 1.8V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 40mA, VHSD1x or VHSD2 x = 0V to 400mV (see Figure 3, Note 13) rON Matching Between Channels, VDD = 1.8V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 40mA, rON (High-Speed) VHSD1x or VHSD2 x = Voltage at max rON, (Notes 12, 13) rON Flatness, RFLAT(ON) (High-Speed) OFF Leakage Current, IHSD1x(OFF) VDD = 1.8V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 40mA, VHSD1x or VHSD2 x = 0V to 400mV, (Notes 11, 13) VDD = 3.3V, SEL = VDD and OE = 0V or OE = VDD, VDx = 0.3V, 3V, VHSD1X = 3V, 0.3V, VHSD2x = 0.3V, 3V
ON Leakage Current, IHSD1x(ON) VDD = 3.3V, SEL = OE = 0V, VDx = 0.3V, 3V, VHSD1X = 0.3V, 3V, VHSD2x = 3V, 0.3V OFF Leakage Current, IHSD2x(OFF) VDD = 3.3V, SEL = OE = 0V or OE = VDD, VDx = 3V, 0.3V, VHSD2x = 0.3V, 3V, VHSD1X = 3V, 0.3V
ON Leakage Current, IHSD2x(ON) VDD = 3.3V, SEL = VDD, OE = 0V, VDx = 0.3V, 3V, VHSD2x = 0.3V, 3V, VHSD1X = 3V, 0.3V Power OFF Leakage Current, IOFF VDD = 0V, VD+ = 0V to 5.25V, VD-= 0V to 5.25V
3
FN6835.1 May 27, 2009
ISL54222
Electrical Specifications - 1.8V to 3.3V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V,
VOEH = 1.4V, VOEL = 0.5V, (Note 8), Unless Otherwise Specified. (Continued) PARAMETER TEST CONDITIONS TEMP MIN (C) (Notes 9, 10) 25 25 25 TYP 12 42 75 MAX (Notes 9, 10) UNITS ns ns ns
Break-Before-Make Time Delay, tD VDD = 3.3V, VIN = 3V, RL = 50, CL = 50pF (see Figure 2) Turn-ON Enable Time, tENABLE VDD = 3.3V, VIN = 3V, RL = 15k, CL = 50pF, Time out of All-Off state
Turn-OFF Disable Time, tDISABLE VDD = 3.3V, VIN = 3V, RL = 15k, CL = 50pF, Time into All-Off state, Time is highly dependent on the load (RL, CL) time constant. Skew, (tSKEWOUT - tSKEWIN) VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, RL = 45, CL = 10pF, tR = tF = 500ps at 480Mbps, (Duty Cycle = 50%) (see Figure 6) VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, RL = 45, CL = 10pF, (see Figure 6) VDD = 3.3V, RL = 50, f = 240MHz (see Figure 5) VDD = 3.3V, OE = 3.3V, RL = 50, f = 240MHz Signal = 0dBm, 0.2VDC offset, RL = 50 f = 1MHz, VDD = 3.3V, SEL = 0V, OE = 3.3V, VHSD1x or VHSD2x = VDx = 0V (see Figure 4) f = 1MHz, VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, VHSD1x or VHSD2x = VDx = 0V (see Figure 4)
25
-
53
-
ps
Rise/Fall Degradation (Propagation Delay), tPD Crosstalk OFF-Isolation -3dB Bandwidth OFF Capacitance, CHSxOFF COM ON Capacitance, CDX(ON)
25 25 25 25 25 25
-
250 -25 -27 782 2.5 6.5
-
ps dB dB MHz pF pF
POWER SUPPLY CHARACTERISTICS Power Supply Range, VDD Positive Supply Current, IDD VDD = 3.3V, SEL = 0V or VDD, OE = 0V or VDD Full 25 Full Positive Supply Current, IDD VDD = 1.8V, SEL = 0V, OE = 0V or VDD 25 Full DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VSELL, VOEL VDD = 1.8V to 3.3V Full Full Full Full Full 1.4 104 -1.5 -1.6 0.5 VDD V V nA nA nA 1.8 32 5.8 3.3 40 50 7.5 8 V A A A A
Input Voltage High, VSELH, VOEH VDD = 1.8V to 3.3V Input Current, ISELL, IOEL Input Current, ISELH Input Current, IOEH NOTES: 8. VLOGIC = Input voltage to perform proper function. VDD = 3.3V, SEL = 0V, OE = 0V VDD = 3.3V, SEL = 3.3V VDD = 3.3V, OE = 3.3V
9. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 10. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 11. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range. 12. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value, between HSD2+ and HSD2- or between HSD1+ and HSD1-. 13. Limits established by characterization and are not production tested.
4
FN6835.1 May 27, 2009
ISL54222 Test Circuits and Waveforms
VDD LOGIC INPUT 50% 0V tOFF SWITCH INPUT VINPUT 90% SWITCH OUTPUT 0V tON VOUT 90% VIN VINPUT SWITCH INPUT HSDxx Dx SEL GND OE RL CL VOUT tr < 20ns tf < 20ns VDD C
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (INPUT) ----------------------R L + r ON FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES
VDD
C
LOGIC INPUT
VDD 0V VINPUT HSD2x HSD1x SEL Dx RL VOUT CL
SWITCH OUTPUT VOUT
90% VIN 0V tD GND
OE
Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 2A. MEASUREMENT POINTS FIGURE 2. BREAK-BEFORE-MAKE TIME
VDD C
FIGURE 2B. TEST CIRCUIT
rON = V1/40mA
HSDx
VHSDX V1 40mA SEL OV OR VDD
Dx
GND
OE
Repeat test for all switches.
FIGURE 3. rON TEST CIRCUIT
5
FN6835.1 May 27, 2009
ISL54222 Test Circuits and Waveforms (Continued)
VDD C VDD C
HSDxx
SIGNAL GENERATOR SEL
HSD1x
Dx
50
IMPEDANCE ANALYZER Dx GND OE
SEL 0V OR VDD VIN
ANALYZER RL Repeat test for all switches.
Dx GND
HSD2x OE
NC
Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches.
FIGURE 4. CAPACITANCE TEST CIRCUIT
FIGURE 5. CROSSTALK TEST CIRCUIT
VDD
C
tri 90% DIN+ DIN10% 50% tskew_i 90% 50% 10% tfi tro 90% OUT+ OUT10% 50% tskew_o 90% tf0 50% 10% GND |tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals. |tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals |tskew_0| Change in Skew through the Switch for Output Signals. |tskew_i| Change in Skew through the Switch for Input Signals. DINDIN+ 143 15.8 143 COMD1 OE D1 CL VIN 15.8 SEL COMD2 D2 CL OUT+ 45 OUT45
FIGURE 6A. MEASUREMENT POINTS FIGURE 6. SKEW TEST
FIGURE 6B. TEST CIRCUIT
6
FN6835.1 May 27, 2009
ISL54222 Application Block Diagram
CONTROLLER VDD
ISL54222
SEL VBUS USB CONNECTOR LOGIC CIRCUITRY
OE
D-
HSD1DHSD1+
USB HIGH-SPEED OR FULL-SPEED TRANSCEIVER #1 USB HIGH_SPEED OR FULL-SPEED TRANSCEIVER #2 PORTABLE MEDIA DEVICE
D+
D+
HSD2HSD2+ GND
GND
Detailed Description
The ISL54222 device is a dual single pole/double throw (SPDT) analog switch configured as a DPDT that operates from a single DC power supply in the range of 1.8V to 3.3V. It was designed to function as a dual 2-to-1 multiplexer to select between two USB high-speed differential data signals in portable battery powered products. It is offered in a TDFN, MSOP, and a small TQFN packages for use in MP3 players, cameras, PDAs, cellphones, and other personal media players. The device has an enable pin to open all switches. The part consists of four 5.5 high speed (HSx) switches. These switches have high bandwidth and low capacitance to pass USB high-speed (480Mbps) differential data signals with minimal edge and phase distortion. They can also swing from 0V to VDD to pass USB full speed (12Mbps) differential data signals with minimal distortion. The ISL54222 was designed for MP3 players, cameras, cellphones, and other personal media player applications that have multiple high-speed or full-speed transceivers sections and need to multiplex between these USB sources to a single USB host (computer). A typical application block diagram of this functionality is previously shown. A detailed description of the HS switches is provided in the following section.
high speed signal transitions. As the signal level increases, the rON switch resistance increases. At signal level of 1.8V, the switch resistance is nominally 12. See Figures 7, 8, 9, 10, 11, 12 in the "Typical Performance Curves" beginning on page 9. The HSx switches were specifically designed to pass USB 2.0 high-speed (480Mbps) differential signals in the range of 0V to 400mV. They have low capacitance (6.5pF) and high bandwidth to pass the USB high-speed signals with minimum edge and phase distortion to meet USB 2.0 high speed signal quality specifications. See Figure 13 in the "Typical Performance Curves" on page 10 for USB High-speed Eye Pattern taken with switches in the differential signal paths. The HSx switches can also pass USB full-speed signals (12Mbps) with minimal distortion and meet all the USB requirements for USB 2.0 full-speed signaling. See Figure 14 and 15 in the "Typical Performance Curves" on page 11 for USB Full-speed Eye Pattern taken with switches in the differential signal paths. The maximum normal operating signal range for the HSx switches is from 0V to VDD. The signal voltage should not be allow to exceed the VDD voltage rail or go below ground by more than -0.3V for normal operation. However, in the event that the USB 5.25V VBUS voltage gets shorted to one or both of the D-/D+ pins, the ISL54222 has special fault protection circuitry to prevent damage to the ISL54222 part. The fault circuitry allows the signal pins (D-, D+, HSD1-, HSD1+, HSD2-, HSD2+) to be driven up to 5.5V while the VDD supply voltage is in the range of 0V to 3.3V. In this condition the part draws < 300A of IDD current and causes no stress to the IC. In addition when VDD is at 0V (ground) all switches are OFF and the fault voltage is isolated from the other side of the switch. When VDD is in the
FN6835.1 May 27, 2009
High-Speed (HSx) Switches
The HSx switches (HSD1-, HSD1+, HSD2-, HSD2+) are bi-directional switches that can pass rail-to-rail signals. When powered with a 1.8V supply, these switches have a nominal rON of 5.5 over the signal range of 0V to 400mV with a rON flatness of 0.44. The rON matching between the HSD1 and HSD2 switches over this signal range is only 0.072, ensuring minimal impact by the switches to USB 7
ISL54222
range of 1.8V to 3.3V the fault voltage will pass through to the output of an active switch channel. During the fault condition normal operation is not guaranteed until the fault is removed. See the "USB 2.0 VBUS Short Requirements" section below. The HS1 channel switches are active (turned ON) whenever the SEL voltage is Logic "0" (Low) and the OE voltage is Logic "0"(Low). The HS2 channel switches are active (turned ON) whenever the SEL voltage is Logic "1" (High) and the OE voltage is Logic "0" (Low). When a computer or USB hub is plugged into the common USB connector and Channel 1 is active, a link will be established between the USB 1 transceiver section of the media player and the computer. The device will be able to transmit and receive data from the computer. HSD2 USB Channel If the SEL pin = Logic "1" and the OE pin = Logic "0", high-speed Channel 2 will be ON. The HSD2- and HSD2+ switches are ON and the HSD1- and HSD1+ switches are OFF (high impedance). When a USB cable from a computer or USB hub is connected at the common USB connector and Channel 2 is active, a link will be established between the USB 2 transceiver section of the media player and the computer. The device will be able to transmit and receive data from the computer. All Switches OFF Mode If the SEL pin = Logic "0" or Logic "1" and the OE pin = Logic "1", all of the switches will turn OFF (high impedance). The "All OFF" state can be used to switch between the two USB sections of the media player. When switching from one USB transceiver section to the other USB transceiver section, you can momentarily put the ISL54222 switch in the "ALL OFF" state, in order to get the computer to disconnect from the current USB section, so it can properly connect to the other USB transceiver section when that channel is turned ON.
ISL54222 Operation
The following will discuss using the ISL54222 shown in the "Application Block Diagram" on page 7. POWER The power supply connected at the VDD pin provides the DC bias voltage required by the ISL54222 part for proper operation. The ISL54222 can be operated with a VDD voltage in the range of 1.8V to 3.3V. A 0.01F or 0.1F decoupling capacitor should be connected from the VDD pin to ground to filter out any power supply noise from entering the part. The capacitor should be located as close to the VDD pin as possible. LOGIC CONTROL The state of the ISL54222 device is determined by the voltage at the SEL pin and the OE pin. SEL is only active when the OE pin is Logic "0" (Low). Refer to the "Truth Table" on page 2. The ISL54222 logic pins are designed to minimize current consumption when the logic control voltage is lower than the VDD supply voltage. With VDD = 3.3V and logic pins at 1.4V the part typically draws only 35A of IDD current. With VDD = 1.8V and logic pins at 1.4V the part typically draws only 6A of IDD current. Driving the logic pins to the VDD supply rail minimizes power consumption. The logic pins must be held High or Low and must not float. Logic Control Voltage Levels With VDD supply voltage in the range of 1.8V to 3.3V the logic levels are: OE = Logic "0" (Low) when VOE 0.5V OE = Logic "1" (High) when VOE 1.4V SEL = Logic "0" (Low) when VSEL 0.5V SEL = Logic "1" (High) when VSEL 1.4V HSD1 USB Channel If the SEL pin = Logic "0" and the OE pin = Logic "0", high-speed Channel 1 will be ON. The HSD1- and HSD1+ switches are ON and the HSD2- and HSD2+ switches are OFF (high impedance).
USB 2.0 VBUS Short Requirements
The USB 2.0 specification in chapter 7, section 7.1.1 states a USB device must be able to withstand a VBUS short to the D+ or D- signal lines when the device is either powered off or powered on for at least 24 hours. The ISL54222 part has special fault protection circuitry to meet these short circuit requirements. The fault protection circuitry allows the signal pins (D-, D+, HSD1-, HSD1+, HSD2-, HSD2+) to be driven up to 5.5V while the VDD supply voltage is in the range of 0V to 3.3V. In this overvoltage condition the part draws < 300A of IDD current and causes no stress/damage to the IC. In addition when VDD is at 0V (ground), all switches are OFF and the shorted VBUS voltage is isolated from the other side of the switch. When VDD is in the range of 1.8V to 3.3V, the shorted VBUS voltage will pass through to the output of an active (turned ON) switch channel but not through a turned OFF channel. Any components connected on the active channel must be able to withstand the overvoltage condition. Note: During the fault condition normal operation of the USB channel is not guaranteed until the fault condition is removed.
8
FN6835.1 May 27, 2009
ISL54222 Typical Performance Curves TA = +25C, Unless Otherwise Specified
6.0 ICOM = 40mA 5.5 1.8V 5.0 rON () 2.7V rON () 10 2.7V 3.0V 3.3V 12 1.8V 14 ICOM = 1mA
4.5
8
4.0
3.3V 3.0V
6
3.5
4
3.0 0
2 0.1 0.2 VCOM (V) 0.3 0.4 0 0.5 1.0 1.5 VCOM (V) 2.0 2.5 3.0 3.3
FIGURE 7. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
8 V+ = 1.8V ICOM = 40mA 7 +85C 6
FIGURE 8. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
16 14 12 10 V+ = 1.8V ICOM = 1mA
rON ()
5
+25C
rON ()
+85C +25C
8 6 4
4
-40C
-40C
3 2 2 0 0
0.1
0.2 VCOM (V)
0.3
0.4
0
0.2
0.4
0.6
0.8 1.0 VCOM (V)
1.2
1.4
1.6
1.8
FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE
5.5 5.0 4.5 rON () 4.0 +25C 3.5 3.0 2.5 2.0 0 0.1 0.2 VCOM (V) 0.3 0.4 -40C V+ = 3.3V ICOM = 40mA
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
9 8
V+ = 3.3V ICOM = 1mA
+85C
7 6 rON () 5 4 3 2 1 0 0 0.5 1.0 1.5 VCOM (V) 2.0 2.5 3.0 3.3 -40C +85C +25C
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
9
FN6835.1 May 27, 2009
ISL54222 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
VDD = 1.8V
VOLTAGE SCALE (0.1V/DIV)
TIME SCALE (0.2ns/DIV)
FIGURE 13. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH
10
FN6835.1 May 27, 2009
ISL54222 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
VDD = 1.8V
VOLTAGE SCALE (0.5V/DIV)
TIME SCALE (10ns/DIV)
FIGURE 14. EYE PATTERN: 12Mbps WITH USB SWITCHES IN THE SIGNAL PATH
VDD = 3.3V
VOLTAGE SCALE (0.5V/DIV)
TIME SCALE (10ns/DIV)
FIGURE 15. EYE PATTERN: 12Mbps WITH USB SWITCHES IN THE SIGNAL PATH
11
FN6835.1 May 27, 2009
ISL54222 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
1 0 -1 -2 NORMALIZED GAIN (dB) -3 -4 NORMALIZED GAIN (dB) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 1k RL = 50 VIN = 0dBm, 0.2VDC BIAS
RL = 50 VIN = 0dBm, 0.2VDC BIAS
1M
10M
100M
1G
10k
100k
1M
10M
100M
500M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 16. FREQUENCY RESPONSE
-10 -20 -30 NORMALIZED GAIN (dB) -40 -50 -60 -70 -80 -90 -100 -110 1k 10k 100k 1M 10M 100M 500M RL = 50 VIN = 0dBm, 0.2VDC BIAS
FIGURE 17. OFF-ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 325 PROCESS: Submicron CMOS
FREQUENCY (Hz)
FIGURE 18. CROSSTALK
12
FN6835.1 May 27, 2009
ISL54222 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D A B
L10.1.8x1.4A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN 0.45 NOMINAL 0.50 0.127 REF 0.15 1.75 1.35 0.20 1.80 1.40 0.40 BSC 0.35 0.45 0.40 0.50 10 2 3 0 12 0.45 0.55 0.25 1.85 1.45 MAX 0.55 0.05 NOTES 5 2 3 3 4 Rev. 3 6/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions.
6 INDEX AREA 2X 2X 0.10 C
N
E
1 0.10 C
2
A A1
TOP VIEW
A3 b
0.10 C 0.05 C SEATING PLANE A1 SIDE VIEW A
D
C
E e L L1 N
(DATUM A) PIN #1 ID L1 NX L 1 2 NX b 5 10X 0.10 M C A B 0.05 M C 5 7 e BOTTOM VIEW (DATUM B)
Nd Ne
NX (b) 5
(A1)
C L
L SECTION "C-C" CC e TERMINAL TIP
9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
1.00
2.20 1.00 0.60
0.50 1.80 0.40 0.20 0.40 10 LAND PATTERN 0.20
13
FN6835.1 May 27, 2009
ISL54222 Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -B12 TOP VIEW 0.25 (0.010) GAUGE PLANE SEATING PLANE -CL L1 4X R1 R 0.20 (0.008) ABC E
INCHES SYMBOL A A1 A2 b c D
4X
MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 4.75 0.40 10 0.07 0.07 5o 0o 15o 6o MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 Rev. 0 12/02
MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 0.187 0.016 10 0.003 0.003 5o 0o
MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120 0.199 0.028
INDEX AREA
E1 e E L L1 N R R1
-B-
A
A2
0.020 BSC
0.50 BSC
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
SIDE VIEW
15o 6o
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
14
FN6835.1 May 27, 2009
ISL54222 Thin Dual Flat No-Lead Plastic Package (TDFN)
2X 0.10 C A A D 2X 0.10 C B
L10.3x3A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1
E
MIN 0.70 -
NOMINAL 0.75 0.20 REF
MAX 0.80 0.05
NOTES -
6 INDEX AREA TOP VIEW B
A3 b D D2 E
// A 0.10 C 0.08 C
0.20 2.95 2.25 2.95 1.45
0.25 3.0 2.30 3.0 1.50 0.50 BSC
0.30 3.05 2.35 3.05 1.55
5, 8 7, 8 7, 8 -
E2 e k
0.25 0.25
0.30 10 5
0.35
8 2 3 Rev. 3 3/06
C SEATING PLANE
SIDE VIEW
A3
L N
D2 (DATUM B) 1 2 D2/2
7
8
Nd NOTES:
6 INDEX AREA (DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
NX k E2 E2/2
2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) L1 9L 5 0.10 M C A B
7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Compliant to JEDEC MO-229-WEED-3 except for D2 dimensions.
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 15
FN6835.1 May 27, 2009

▲Up To Search▲

Price & Availability of ISL5422209

	To Download ISL5422209 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .